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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/SathyamurthySF98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Harsha_Sathyamurthy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_P._Fishburn>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.681267>
foaf:homepage <https://doi.org/10.1109/43.681267>
dc:identifier DBLP journals/tcad/SathyamurthySF98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.681267 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Harsha_Sathyamurthy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_P._Fishburn>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
swrc:number 2 (xsd:string)
swrc:pages 173-182 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/SathyamurthySF98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/SathyamurthySF98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad17.html#SathyamurthySF98>
rdfs:seeAlso <https://doi.org/10.1109/43.681267>
dc:title Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 17 (xsd:string)