TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Anirban_Sengupta>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Saumya_Bhadauria>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2016.2597232>
foaf:homepage	<https://doi.org/10.1109/TCAD.2016.2597232>
dc:identifier	DBLP journals/tcad/SenguptaBM17 (xsd:string)
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dcterms:issued	2017 (xsd:gYear)
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rdfs:label	TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Saumya_Bhadauria>
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swrc:pages	655-668 (xsd:string)
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dc:title	TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. (xsd:string)
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