[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/SoyataFM97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eby_G._Friedman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_H._Mulligan_Jr.>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tolga_Soyata>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.559335>
foaf:homepage <https://doi.org/10.1109/43.559335>
dc:identifier DBLP journals/tcad/SoyataFM97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.559335 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Incorporating interconnect, register, and clock distribution delays into the retiming process. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eby_G._Friedman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_H._Mulligan_Jr.>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tolga_Soyata>
swrc:number 1 (xsd:string)
swrc:pages 105-120 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/SoyataFM97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/SoyataFM97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#SoyataFM97>
rdfs:seeAlso <https://doi.org/10.1109/43.559335>
dc:title Incorporating interconnect, register, and clock distribution delays into the retiming process. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)