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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/ThakerAZ03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mona_E._Zaghloul>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pradip_A._Thaker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2003.814958>
foaf:homepage <https://doi.org/10.1109/TCAD.2003.814958>
dc:identifier DBLP journals/tcad/ThakerAZ03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2003.814958 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label A test evaluation technique for VLSI circuits using register-transfer level fault modeling. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mona_E._Zaghloul>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pradip_A._Thaker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
swrc:number 8 (xsd:string)
swrc:pages 1104-1113 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/ThakerAZ03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/ThakerAZ03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad22.html#ThakerAZ03>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2003.814958>
dc:title A test evaluation technique for VLSI circuits using register-transfer level fault modeling. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 22 (xsd:string)