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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/WangTJ03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun-Yao_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jing-Yang_Jou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shing-Wu_Tung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2002.805723>
foaf:homepage <https://doi.org/10.1109/TCAD.2002.805723>
dc:identifier DBLP journals/tcad/WangTJ03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2002.805723 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Automatic interconnection rectification for SoC design verification based on the port order fault model. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun-Yao_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jing-Yang_Jou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shing-Wu_Tung>
swrc:number 1 (xsd:string)
swrc:pages 104-114 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/WangTJ03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/WangTJ03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad22.html#WangTJ03>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2002.805723>
dc:title Automatic interconnection rectification for SoC design verification based on the port order fault model. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 22 (xsd:string)