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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/YinGLLW16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dajiang_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiangyuan_Gu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2015.2512900>
foaf:homepage <https://doi.org/10.1109/TCAD.2015.2512900>
dc:identifier DBLP journals/tcad/YinGLLW16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2015.2512900 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dajiang_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiangyuan_Gu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
swrc:number 9 (xsd:string)
swrc:pages 1475-1488 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/YinGLLW16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/YinGLLW16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#YinGLLW16>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2015.2512900>
dc:title Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 35 (xsd:string)