Clock skew minimization during FPGA placement. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/tcad/ZhuW97>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kai_Zhu_0001>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Martin_D._F._Wong>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2F43.602474>
foaf:homepage	<https://doi.org/10.1109/43.602474>
dc:identifier	DBLP journals/tcad/ZhuW97 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2F43.602474 (xsd:string)
dcterms:issued	1997 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label	Clock skew minimization during FPGA placement. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kai_Zhu_0001>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Martin_D._F._Wong>
swrc:number	4 (xsd:string)
swrc:pages	376-385 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/tcad/ZhuW97/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/journals/tcad/ZhuW97>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#ZhuW97>
rdfs:seeAlso	<https://doi.org/10.1109/43.602474>
dc:title	Clock skew minimization during FPGA placement. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:Article
rdf:type	foaf:Document
swrc:volume	16 (xsd:string)