A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/tcas/ArandaRM18>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Juan_Antonio_Maestro>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Luis_Alberto_Aranda>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Pedro_Reviriego>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTCSII.2017.2717490>
foaf:homepage	<https://doi.org/10.1109/TCSII.2017.2717490>
dc:identifier	DBLP journals/tcas/ArandaRM18 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FTCSII.2017.2717490 (xsd:string)
dcterms:issued	2018 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/tcas>
rdfs:label	A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Juan_Antonio_Maestro>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Luis_Alberto_Aranda>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Pedro_Reviriego>
swrc:number	3 (xsd:string)
swrc:pages	376-380 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/tcas/ArandaRM18/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/journals/tcas/ArandaRM18>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tcas/tcasII65.html#ArandaRM18>
rdfs:seeAlso	<https://doi.org/10.1109/TCSII.2017.2717490>
dc:title	A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:Article
rdf:type	foaf:Document
swrc:volume	65-II (xsd:string)