A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tcas/CheangMM18
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tcas/CheangMM18
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chak-Fong_Cheang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Pui-In_Mak
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Rui_Paulo_Martins
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FTCSI.2017.2788082
>
foaf:
homepage
<
https://doi.org/10.1109/TCSI.2017.2788082
>
dc:
identifier
DBLP journals/tcas/CheangMM18
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FTCSI.2017.2788082
(xsd:string)
dcterms:
issued
2018
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tcas
>
rdfs:
label
A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chak-Fong_Cheang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Pui-In_Mak
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Rui_Paulo_Martins
>
swrc:
number
9
(xsd:string)
swrc:
pages
2889-2902
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tcas/CheangMM18/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tcas/CheangMM18
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tcas/tcasI65.html#CheangMM18
>
rdfs:
seeAlso
<
https://doi.org/10.1109/TCSI.2017.2788082
>
dc:
title
A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
65-I
(xsd:string)