A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Indranil_Hatai>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Swapna_Banerjee>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTCSI.2017.2719053>
foaf:homepage	<https://doi.org/10.1109/TCSI.2017.2719053>
dc:identifier	DBLP journals/tcas/HataiCB18 (xsd:string)
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dcterms:issued	2018 (xsd:gYear)
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rdfs:label	A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Indrajit_Chakrabarti>
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Swapna_Banerjee>
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swrc:pages	130-140 (xsd:string)
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dc:title	A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. (xsd:string)
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