A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tcas/ScarselliPPC15
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A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test.
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A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test.
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