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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcas/UpadhyayaS13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bijoy_Kumar_Upadhyaya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Salil_Kumar_Sanyal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCSII.2013.2268372>
foaf:homepage <https://doi.org/10.1109/TCSII.2013.2268372>
dc:identifier DBLP journals/tcas/UpadhyayaS13 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCSII.2013.2268372 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcas>
rdfs:label Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bijoy_Kumar_Upadhyaya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Salil_Kumar_Sanyal>
swrc:number 8 (xsd:string)
swrc:pages 492-496 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcas/UpadhyayaS13/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcas/UpadhyayaS13>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcas/tcasII60.html#UpadhyayaS13>
rdfs:seeAlso <https://doi.org/10.1109/TCSII.2013.2268372>
dc:title Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 60-II (xsd:string)