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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcasII/BalSKD22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ankur_Bal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aradhana_Kumari>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rupesh_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vikas_Dhanda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCSII.2022.3185499>
foaf:homepage <https://doi.org/10.1109/TCSII.2022.3185499>
dc:identifier DBLP journals/tcasII/BalSKD22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCSII.2022.3185499 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcasII>
rdfs:label A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ankur_Bal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aradhana_Kumari>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rupesh_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vikas_Dhanda>
swrc:number 10 (xsd:string)
swrc:pages 4073-4077 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcasII/BalSKD22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcasII/BalSKD22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcasII/tcasII69.html#BalSKD22>
rdfs:seeAlso <https://doi.org/10.1109/TCSII.2022.3185499>
dc:title A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 69 (xsd:string)