A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tce/LeeR10
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A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation.
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A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation.
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