A formal method for hardware IP design and integration under I/O and timing constraints.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tecs/CoussyCBBM06
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2006
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A formal method for hardware IP design and integration under I/O and timing constraints.
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dc:
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IP design and integration, SoC, communication interface unit, constrained synthesis, digital signal processing and multimedia applications
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A formal method for hardware IP design and integration under I/O and timing constraints.
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