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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tecs/KrishnaswamyG05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arvind_Krishnaswamy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajiv_Gupta_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1053271.1053273>
foaf:homepage <https://doi.org/10.1145/1053271.1053273>
dc:identifier DBLP journals/tecs/KrishnaswamyG05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1053271.1053273 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tecs>
rdfs:label Dynamic coalescing for 16-bit instructions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arvind_Krishnaswamy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajiv_Gupta_0001>
swrc:number 1 (xsd:string)
swrc:pages 3-37 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tecs/KrishnaswamyG05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tecs/KrishnaswamyG05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tecs/tecs4.html#KrishnaswamyG05>
rdfs:seeAlso <https://doi.org/10.1145/1053271.1053273>
dc:subject 16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, Embedded processor, code size, energy, instruction coalescing, performance (xsd:string)
dc:title Dynamic coalescing for 16-bit instructions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 4 (xsd:string)