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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tecs/KumarD08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dipankar_Das_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajeev_Kumar_0004>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1347375.1347388>
foaf:homepage <https://doi.org/10.1145/1347375.1347388>
dc:identifier DBLP journals/tecs/KumarD08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1347375.1347388 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tecs>
rdfs:label Code compression for performance enhancement of variable-length embedded processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dipankar_Das_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajeev_Kumar_0004>
swrc:number 3 (xsd:string)
swrc:pages 35:1-35:36 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tecs/KumarD08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tecs/KumarD08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tecs/tecs7.html#KumarD08>
rdfs:seeAlso <https://doi.org/10.1145/1347375.1347388>
dc:subject Code compression, RISC processor, bus switching, code decompression, embedded systems, instruction memory, variable-length ISAs (xsd:string)
dc:title Code compression for performance enhancement of variable-length embedded processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 7 (xsd:string)