[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tecs/LeeLPM07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang_Yun_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaejin_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sang_Lyul_Min>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sheayun_Lee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1234675.1234677>
foaf:homepage <https://doi.org/10.1145/1234675.1234677>
dc:identifier DBLP journals/tecs/LeeLPM07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1234675.1234677 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tecs>
rdfs:label Selective code transformation for dual instruction set processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang_Yun_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaejin_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sang_Lyul_Min>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sheayun_Lee>
swrc:number 2 (xsd:string)
swrc:pages 10 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tecs/LeeLPM07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tecs/LeeLPM07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tecs/tecs6.html#LeeLPM07>
rdfs:seeAlso <https://doi.org/10.1145/1234675.1234677>
dc:subject Dual instruction set processors, mixed-width instruction set architecture, reduced bid-width instruction set architecture (xsd:string)
dc:title Selective code transformation for dual instruction set processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)