Processor-memory coexploration using an architecture description language.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tecs/MishraMD04
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tecs/MishraMD04
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Mahesh_Mamidipaka
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Nikil_D._Dutt
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Prabhat_Mishra_0001
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http://dx.doi.org/doi.org%2F10.1145%2F972627.972634
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DBLP journals/tecs/MishraMD04
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DOI doi.org%2F10.1145%2F972627.972634
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dcterms:
issued
2004
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swrc:
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rdfs:
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Processor-memory coexploration using an architecture description language.
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swrc:
number
1
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swrc:
pages
140-162
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rdfs:
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dc:
subject
Processor--memory codesign, architecture description language, design space exploration, memory exploration
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dc:
title
Processor-memory coexploration using an architecture description language.
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3
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