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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tecs/TuliLSJ23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chia-Hao_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ritvik_Sharma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shikhar_Tuli>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3575798>
foaf:homepage <https://doi.org/10.1145/3575798>
dc:identifier DBLP journals/tecs/TuliLSJ23 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3575798 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tecs>
rdfs:label CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chia-Hao_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ritvik_Sharma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shikhar_Tuli>
swrc:number 3 (xsd:string)
swrc:pages 51:1-51:30 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tecs/TuliLSJ23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tecs/TuliLSJ23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tecs/tecs22.html#TuliLSJ23>
rdfs:seeAlso <https://doi.org/10.1145/3575798>
dc:title CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 22 (xsd:string)