Parallelizing load/stores on dual-bank memory embedded processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tecs/ZhuangP06
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https://dblp.l3s.de/d2r/resource/authors/Xiaotong_Zhuang
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2006
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Parallelizing load/stores on dual-bank memory embedded processors.
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3
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613-657
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dc:
subject
DSP architectures, memory bank allocation, parallel load/stores, profile driven optimization
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title
Parallelizing load/stores on dual-bank memory embedded processors.
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