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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tecs/ZhuangP06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Santosh_Pande>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaotong_Zhuang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1165780.1165784>
foaf:homepage <https://doi.org/10.1145/1165780.1165784>
dc:identifier DBLP journals/tecs/ZhuangP06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1165780.1165784 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tecs>
rdfs:label Parallelizing load/stores on dual-bank memory embedded processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Santosh_Pande>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaotong_Zhuang>
swrc:number 3 (xsd:string)
swrc:pages 613-657 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tecs/ZhuangP06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tecs/ZhuangP06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tecs/tecs5.html#ZhuangP06>
rdfs:seeAlso <https://doi.org/10.1145/1165780.1165784>
dc:subject DSP architectures, memory bank allocation, parallel load/stores, profile driven optimization (xsd:string)
dc:title Parallelizing load/stores on dual-bank memory embedded processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 5 (xsd:string)