Performance study of an input and output queueing ATM switch with a window scheme and a speed constraint.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/telsys/ChoiU96
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Jin_Seek_Choi
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1996
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Performance study of an input and output queueing ATM switch with a window scheme and a speed constraint.
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dc:
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Performance study of an input and output queueing ATM switch with a window scheme and a speed constraint.
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