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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tetc/CuiLWNP18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ji_Li_0006>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massoud_Pedram>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shahin_Nazarian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tiansong_Cui>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yanzhi_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTETC.2016.2640185>
foaf:homepage <https://doi.org/10.1109/TETC.2016.2640185>
dc:identifier DBLP journals/tetc/CuiLWNP18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTETC.2016.2640185 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tetc>
rdfs:label An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ji_Li_0006>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massoud_Pedram>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shahin_Nazarian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tiansong_Cui>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yanzhi_Wang>
swrc:number 2 (xsd:string)
swrc:pages 172-183 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tetc/CuiLWNP18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tetc/CuiLWNP18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tetc/tetc6.html#CuiLWNP18>
rdfs:seeAlso <https://doi.org/10.1109/TETC.2016.2640185>
dc:title An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)