Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tetc/EnachescuLVC18
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tetc/EnachescuLVC18
>
dc:
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https://dblp.l3s.de/d2r/resource/authors/George_Razvan_Voicu
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https://dblp.l3s.de/d2r/resource/authors/Marius_Enachescu
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Mihai_Lefter
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Sorin_Dan_Cotofana
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foaf:
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http://dx.doi.org/doi.org%2F10.1109%2FTETC.2016.2588725
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dc:
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DBLP journals/tetc/EnachescuLVC18
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dc:
identifier
DOI doi.org%2F10.1109%2FTETC.2016.2588725
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dcterms:
issued
2018
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swrc:
journal
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https://dblp.l3s.de/d2r/resource/journals/tetc
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rdfs:
label
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory.
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foaf:
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https://dblp.l3s.de/d2r/resource/authors/George_Razvan_Voicu
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foaf:
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foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sorin_Dan_Cotofana
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swrc:
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2
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swrc:
pages
184-199
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rdfs:
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http://dblp.uni-trier.de/db/journals/tetc/tetc6.html#EnachescuLVC18
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https://doi.org/10.1109/TETC.2016.2588725
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dc:
title
Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory.
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