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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tetc/Rangel-PatinoVR20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andres_Viveros-Wacher>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Edgar-Andrei_Vega-Ochoa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrique_Lopez-Miralrio>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francisco_E._Rangel-Patino>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ismael_Duron-Rosales>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Ernesto_Rayas-S%E2%88%9A%C2%B0nchez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nagib_Hakim>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTETC.2017.2757937>
foaf:homepage <https://doi.org/10.1109/TETC.2017.2757937>
dc:identifier DBLP journals/tetc/Rangel-PatinoVR20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTETC.2017.2757937 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tetc>
rdfs:label A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andres_Viveros-Wacher>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Edgar-Andrei_Vega-Ochoa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrique_Lopez-Miralrio>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francisco_E._Rangel-Patino>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ismael_Duron-Rosales>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Ernesto_Rayas-S%E2%88%9A%C2%B0nchez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nagib_Hakim>
swrc:number 2 (xsd:string)
swrc:pages 453-463 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tetc/Rangel-PatinoVR20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tetc/Rangel-PatinoVR20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tetc/tetc8.html#Rangel-PatinoVR20>
rdfs:seeAlso <https://doi.org/10.1109/TETC.2017.2757937>
dc:title A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 8 (xsd:string)