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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tie/VachhaniS08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._Sridharan_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leena_Vachhani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTIE.2008.917161>
foaf:homepage <https://doi.org/10.1109/TIE.2008.917161>
dc:identifier DBLP journals/tie/VachhaniS08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTIE.2008.917161 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tie>
rdfs:label Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._Sridharan_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leena_Vachhani>
swrc:number 4 (xsd:string)
swrc:pages 1558-1569 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tie/VachhaniS08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tie/VachhaniS08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tie/tie55.html#VachhaniS08>
rdfs:seeAlso <https://doi.org/10.1109/TIE.2008.917161>
dc:title Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 55 (xsd:string)