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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tim/FengPCP10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Minsu_Choi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Noh-Jin_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nohpill_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tao_Feng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTIM.2009.2030917>
foaf:homepage <https://doi.org/10.1109/TIM.2009.2030917>
dc:identifier DBLP journals/tim/FengPCP10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTIM.2009.2030917 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tim>
rdfs:label Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Minsu_Choi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Noh-Jin_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nohpill_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tao_Feng>
swrc:number 7 (xsd:string)
swrc:pages 1812-1824 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tim/FengPCP10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tim/FengPCP10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tim/tim59.html#FengPCP10>
rdfs:seeAlso <https://doi.org/10.1109/TIM.2009.2030917>
dc:title Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 59 (xsd:string)