An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tim/Parsakordasiabi22
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An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA.
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An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA.
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