Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tim/TaylorNCLCSHHB05
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Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement.
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Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement.
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