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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tjs/AbderazekYS06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ben_A._Abderazek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Sowa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Yoshinaga>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11227-006-6719-5>
foaf:homepage <https://doi.org/10.1007/s11227-006-6719-5>
dc:identifier DBLP journals/tjs/AbderazekYS06 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11227-006-6719-5 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tjs>
rdfs:label High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ben_A._Abderazek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Sowa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Yoshinaga>
swrc:number 1 (xsd:string)
swrc:pages 3-15 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tjs/AbderazekYS06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tjs/AbderazekYS06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tjs/tjs38.html#AbderazekYS06>
rdfs:seeAlso <https://doi.org/10.1007/s11227-006-6719-5>
dc:subject prototyping; queue processor; high performance; design; high-level modeling (xsd:string)
dc:title High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 38 (xsd:string)