An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tjs/FloresAA08
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2008
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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.
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3
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341-364
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Chip-multiprocessor; Power dissipation model; Microarchitectural level simulator; Heterogeneus on-chip interconnection network; Parallel scientific applications
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An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.
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45
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