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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tjs/KittitornkunH03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Surin_Kittitornkun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Hen_Hu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1022028729196>
foaf:homepage <https://doi.org/10.1023/A:1022028729196>
dc:identifier DBLP journals/tjs/KittitornkunH03 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1022028729196 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tjs>
rdfs:label Processor Array Synthesis from Shift-Variant Deep Nested Do Loops. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Surin_Kittitornkun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Hen_Hu>
swrc:number 3 (xsd:string)
swrc:pages 229-249 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tjs/KittitornkunH03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tjs/KittitornkunH03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tjs/tjs24.html#KittitornkunH03>
rdfs:seeAlso <https://doi.org/10.1023/A:1022028729196>
dc:subject reconfigurable computing; FPGA; nested loop; systolic mapping; motion estimation (xsd:string)
dc:title Processor Array Synthesis from Shift-Variant Deep Nested Do Loops. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 24 (xsd:string)