Design and evaluation of a hierarchical decoupled architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tjs/RoCDG06
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tjs/RoCDG06
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Alvin_M._Despain
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jean-Luc_Gaudiot
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Stephen_P._Crago
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Won_Woo_Ro
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2Fs11227-006-8321-2
>
foaf:
homepage
<
https://doi.org/10.1007/s11227-006-8321-2
>
dc:
identifier
DBLP journals/tjs/RoCDG06
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2Fs11227-006-8321-2
(xsd:string)
dcterms:
issued
2006
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tjs
>
rdfs:
label
Design and evaluation of a hierarchical decoupled architecture.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Alvin_M._Despain
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jean-Luc_Gaudiot
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Stephen_P._Crago
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Won_Woo_Ro
>
swrc:
number
3
(xsd:string)
swrc:
pages
237-259
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tjs/RoCDG06/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tjs/RoCDG06
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tjs/tjs38.html#RoCDG06
>
rdfs:
seeAlso
<
https://doi.org/10.1007/s11227-006-8321-2
>
dc:
subject
Decoupled architectures; Memory latency hiding; Multithreading; Parallel architecture; Instruction level parallelism; Data prefetching; Speculative execution
(xsd:string)
dc:
title
Design and evaluation of a hierarchical decoupled architecture.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
38
(xsd:string)