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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tjs/TosiniVL24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lucas_Leiva>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcelo_Tosini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mart%E2%88%9A%E2%89%A0n_V%E2%88%9A%C2%B0zquez_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11227-023-05808-w>
foaf:homepage <https://doi.org/10.1007/s11227-023-05808-w>
dc:identifier DBLP journals/tjs/TosiniVL24 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11227-023-05808-w (xsd:string)
dcterms:issued 2024 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tjs>
rdfs:label Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lucas_Leiva>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcelo_Tosini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mart%E2%88%9A%E2%89%A0n_V%E2%88%9A%C2%B0zquez_0001>
swrc:month May (xsd:string)
swrc:number 7 (xsd:string)
swrc:pages 9298-9326 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tjs/TosiniVL24/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tjs/TosiniVL24>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tjs/tjs80.html#TosiniVL24>
rdfs:seeAlso <https://doi.org/10.1007/s11227-023-05808-w>
dc:title Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 80 (xsd:string)