Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tjs/YangL05
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2005
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Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator.
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dc:
subject
validation; cycle-accurate; retargetable; instruction-set simulator; architecture description language (ADL); system-on-chip (SoC)
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Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator.
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