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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tmscs/LinSLFZ18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hao_Liang_0003>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Liang_Feng_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharad_Sinha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Zhang_0012>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhe_Lin_0007>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTMSCS.2017.2754378>
foaf:homepage <https://doi.org/10.1109/TMSCS.2017.2754378>
dc:identifier DBLP journals/tmscs/LinSLFZ18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTMSCS.2017.2754378 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tmscs>
rdfs:label Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hao_Liang_0003>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Liang_Feng_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharad_Sinha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Zhang_0012>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhe_Lin_0007>
swrc:number 2 (xsd:string)
swrc:pages 152-162 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tmscs/LinSLFZ18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tmscs/LinSLFZ18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tmscs/tmscs4.html#LinSLFZ18>
rdfs:seeAlso <https://doi.org/10.1109/TMSCS.2017.2754378>
dc:title Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 4 (xsd:string)