Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/tnn/Hafliger07>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Philipp_H%E2%88%9A%C2%A7fliger>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTNN.2006.884676>
foaf:homepage	<https://doi.org/10.1109/TNN.2006.884676>
dc:identifier	DBLP journals/tnn/Hafliger07 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FTNN.2006.884676 (xsd:string)
dcterms:issued	2007 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/tnn>
rdfs:label	Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Philipp_H%E2%88%9A%C2%A7fliger>
swrc:number	2 (xsd:string)
swrc:pages	551-572 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tnn/tnn18.html#Hafliger07>
rdfs:seeAlso	<https://doi.org/10.1109/TNN.2006.884676>
dc:title	Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip. (xsd:string)
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rdf:type	swrc:Article
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swrc:volume	18 (xsd:string)