Using complete-1-distinguishability for FSM equivalence checking.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/AsharGM01
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Aarti_Gupta
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Pranav_Ashar
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https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik
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DBLP journals/todaes/AsharGM01
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dc:
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DOI doi.org%2F10.1145%2F502175.502183
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2001
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swrc:
journal
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Using complete-1-distinguishability for FSM equivalence checking.
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4
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swrc:
pages
569-590
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rdfs:
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dc:
subject
Bisimulation relation, complete-1-distinguishability, equivalence checking, finite state machine equivalence, sequential logic synthesis
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title
Using complete-1-distinguishability for FSM equivalence checking.
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6
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