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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/BoyerASB01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/El_Mostapha_Aboulhamid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_R._Boyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michel_Boyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F502175.502180>
foaf:homepage <https://doi.org/10.1145/502175.502180>
dc:identifier DBLP journals/todaes/BoyerASB01 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F502175.502180 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Optimal design of synchronous circuits using software pipelining techniques. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/El_Mostapha_Aboulhamid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_R._Boyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michel_Boyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
swrc:number 4 (xsd:string)
swrc:pages 516-532 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/BoyerASB01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/BoyerASB01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes6.html#BoyerASB01>
rdfs:seeAlso <https://doi.org/10.1145/502175.502180>
dc:subject Resynthesis, retiming, software pipelining (xsd:string)
dc:title Optimal design of synchronous circuits using software pipelining techniques. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)