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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/ChabiniACS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/El_Mostapha_Aboulhamid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Isma%E2%88%9A%C4%AEl_Chabini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Noureddine_Chabini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1059876.1059877>
foaf:homepage <https://doi.org/10.1145/1059876.1059877>
dc:identifier DBLP journals/todaes/ChabiniACS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1059876.1059877 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/El_Mostapha_Aboulhamid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Isma%E2%88%9A%C4%AEl_Chabini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Noureddine_Chabini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yvon_Savaria>
swrc:number 2 (xsd:string)
swrc:pages 187-204 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/ChabiniACS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/ChabiniACS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes10.html#ChabiniACS05>
rdfs:seeAlso <https://doi.org/10.1145/1059876.1059877>
dc:subject Retiming, clock, multiphase, sequential circuit, software pipelining (xsd:string)
dc:title Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 10 (xsd:string)