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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/ChangZW00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._F._Wong_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kai_Zhu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yao-Wen_Chang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F348019.348101>
foaf:homepage <https://doi.org/10.1145/348019.348101>
dc:identifier DBLP journals/todaes/ChangZW00 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F348019.348101 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Timing-driven routing for symmetrical array-based FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._F._Wong_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kai_Zhu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yao-Wen_Chang>
swrc:number 3 (xsd:string)
swrc:pages 433-450 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/ChangZW00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/ChangZW00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes5.html#ChangZW00>
rdfs:seeAlso <https://doi.org/10.1145/348019.348101>
dc:subject computer-aided design of VLSI, field-programmable gate array, layout, synthesis (xsd:string)
dc:title Timing-driven routing for symmetrical array-based FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 5 (xsd:string)