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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/CongH00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yean-Yow_Hwang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F335043.335045>
foaf:homepage <https://doi.org/10.1145/335043.335045>
dc:identifier DBLP journals/todaes/CongH00 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F335043.335045 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yean-Yow_Hwang>
swrc:number 2 (xsd:string)
swrc:pages 193-225 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/CongH00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/CongH00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes5.html#CongH00>
rdfs:seeAlso <https://doi.org/10.1145/335043.335045>
dc:subject FPGA, computer-aided design of VSLI, decomposition, delay minimization, logic optimization, programmable logic, simplification, synthesis, system design, technology mapping (xsd:string)
dc:title Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 5 (xsd:string)