Reusing an on-chip network for the test of core-based systems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/CotaCL04
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2004
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Reusing an on-chip network for the test of core-based systems.
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4
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471-499
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Core-based test, SoC test, TAM and wrapper design, network-on-chip, test reuse, test scheduling
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Reusing an on-chip network for the test of core-based systems.
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