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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/FanLWW02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._K._Wong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hongbing_Fan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiping_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Liang_Wu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F605440.605443>
foaf:homepage <https://doi.org/10.1145/605440.605443>
dc:identifier DBLP journals/todaes/FanLWW02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F605440.605443 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Reduction design for generic universal switch blocks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._K._Wong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hongbing_Fan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiping_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Liang_Wu>
swrc:number 4 (xsd:string)
swrc:pages 526-546 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/FanLWW02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/FanLWW02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes7.html#FanLWW02>
rdfs:seeAlso <https://doi.org/10.1145/605440.605443>
dc:subject FPGA architecture design, decomposition, routing, routing requirement, switch module, universal switch block (xsd:string)
dc:title Reduction design for generic universal switch blocks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 7 (xsd:string)