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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/GulatiPKPJ09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Jas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kanupriya_Gulati>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Patil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Suganth_Paul>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sunil_P._Khatri>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1497561.1497576>
foaf:homepage <https://doi.org/10.1145/1497561.1497576>
dc:identifier DBLP journals/todaes/GulatiPKPJ09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1497561.1497576 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label FPGA-based hardware acceleration for Boolean satisfiability. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Jas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kanupriya_Gulati>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Patil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Suganth_Paul>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sunil_P._Khatri>
swrc:number 2 (xsd:string)
swrc:pages 33:1-33:11 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/GulatiPKPJ09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/GulatiPKPJ09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes14.html#GulatiPKPJ09>
rdfs:seeAlso <https://doi.org/10.1145/1497561.1497576>
dc:subject Boolean satisfiabilty (SAT), FPGA, boolean constant propagation (BCP), conflict induced clauses, non-chronological backtrack (xsd:string)
dc:title FPGA-based hardware acceleration for Boolean satisfiability. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 14 (xsd:string)