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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/HanS18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Inhak_Han>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Youngsoo_Shin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3229082>
foaf:homepage <https://doi.org/10.1145/3229082>
dc:identifier DBLP journals/todaes/HanS18 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3229082 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Inhak_Han>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Youngsoo_Shin>
swrc:number 5 (xsd:string)
swrc:pages 61:1-61:21 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/HanS18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/HanS18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes23.html#HanS18>
rdfs:seeAlso <https://doi.org/10.1145/3229082>
dc:title Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)