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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/JoneWLHC03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hsueh-I_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/I._P._Hsu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J.-Y._Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wen-Ben_Jone>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F606603.606606>
foaf:homepage <https://doi.org/10.1145/606603.606606>
dc:identifier DBLP journals/todaes/JoneWLHC03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F606603.606606 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Design theory and implementation for low-power segmented bus systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hsueh-I_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/I._P._Hsu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J.-Y._Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wen-Ben_Jone>
swrc:number 1 (xsd:string)
swrc:pages 38-54 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/JoneWLHC03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/JoneWLHC03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes8.html#JoneWLHC03>
rdfs:seeAlso <https://doi.org/10.1145/606603.606606>
dc:subject ASIC design, OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design, low-power design flow (xsd:string)
dc:title Design theory and implementation for low-power segmented bus systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 8 (xsd:string)