Implementing the scale vector-thread processor.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/KrashinskyBA08
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/todaes/KrashinskyBA08
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Christopher_Batten
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Krste_Asanovic
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ronny_Krashinsky
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1367045.1367050
>
foaf:
homepage
<
https://doi.org/10.1145/1367045.1367050
>
dc:
identifier
DBLP journals/todaes/KrashinskyBA08
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1367045.1367050
(xsd:string)
dcterms:
issued
2008
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/todaes
>
rdfs:
label
Implementing the scale vector-thread processor.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Christopher_Batten
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Krste_Asanovic
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ronny_Krashinsky
>
swrc:
number
3
(xsd:string)
swrc:
pages
41:1-41:24
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/todaes/KrashinskyBA08/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/todaes/KrashinskyBA08
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/todaes/todaes13.html#KrashinskyBA08
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1367045.1367050
>
dc:
subject
Vector processors, hybrid C++/Verilog simulation, iterative VLSI design flow, multithreaded processors, procedural datapath pre-placement, vector-thread processors
(xsd:string)
dc:
title
Implementing the scale vector-thread processor.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
13
(xsd:string)