Instruction set synthesis with efficient instruction encoding for configurable processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/LeeCD07
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https://dblp.l3s.de/d2r/resource/authors/Kiyoung_Choi
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2007
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Instruction set synthesis with efficient instruction encoding for configurable processors.
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9:1-9:37
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dc:
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Application-specific instruction set processor (ASIP), ISA customization and specialization, bitwidth-economical, configurable processor, instruction encoding
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title
Instruction set synthesis with efficient instruction encoding for configurable processors.
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