On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/LeeCOM07
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bibliographicCitation
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https://dblp.l3s.de/d2r/resource/authors/%E2%88%9A%C3%BAmit_Y._Ogras
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https://dblp.l3s.de/d2r/resource/authors/Hyung_Gyu_Lee
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https://dblp.l3s.de/d2r/resource/authors/Naehyuck_Chang
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https://dblp.l3s.de/d2r/resource/authors/Radu_Marculescu
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2007
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swrc:
journal
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rdfs:
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On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.
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dc:
subject
FPGA prototype, MPEG-2 encoder, Networks-on-chip, point-to-point, system-on-chip
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dc:
title
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.
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